DS1213B smartsocket 16k/64k DS1213B 031998 1/6 features ? accepts standard 2k x 8 or 8k x 8 cmos static rams ? embedded lithium energy cell retains ram data ? selfcontained circuitry safeguards data ? data retention time is greater than 10 years with the proper ram selection ? ic socket permits upgrading from 2k x 8 to 8k x 8 ram ? proven gastight socket contacts ? operating temperature range 0 c to 70 c pin assignment 28pin intelligent socket 1 2 3 4 5 6 7 8 9 10 11 12 13 gnd 14 28 v cc 27 26 v cc 25 24 23 22 21 20 ce 19 18 17 16 15 pin description ce conditioned chip enable v cc switched v cc gnd ground all pins pass through except 20, 26 and 28. description the DS1213B smartsocket is a 28pin, 600 mil dip socket with a builtin cmos controller circuit and an embedded lithium energy source. it accepts either 24pin 2k x 8 (lowerjustified) or 28pin 8k x 8 jedec bytewide cmos static ram. when the socket is mated with a cmos ram, it provides a complete solution to problems associated with memory volatility. the smart- socket monitors incoming v cc for an outoftolerance condition. when such a condition occurs, the internal lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. using the smartsocket saves printed circuit board space since the sram/smartsocket combination occu- pies no more area than the sram alone. the smart- socket modifies only pins 20, 26 and 28, to nonvolatize the ram. all other pins are passed straight through.
DS1213B 031998 2/6 operation the DS1213B smartsocket performs five circuit func- tions required to battery back up a cmos memory. the first function involves switching between the battery and the v cc supply, depending on which is greater. the switch has a voltage drop of less than 0.2 volts. the second function is powerfail detection. the DS1213B constantly monitors the v cc supply. when v cc falls below 4.75 volts, a precision comparator de- tects the condition and inhibits the ram chip enable. the third function, write protection, is accomplished by holding the ram chip enable signal to within 0.2 volts of v cc or the battery supply whichever is greater. if the incoming chip enable signal is active at the time power fail detection occurs, write protection is delayed until af- ter the current memory cycle is complete to avoid cor- ruption of data. power fail detection occurs in the range of 4.75 to 4.5 volts. during nominal power supply condi- tions the chip enable signal will be passed through from the socket pin to the socket contact with a maximum propagation delay of 20 ns. the fourth function the DS1213B performs is to check battery status to warn of potential data loss. each time that v cc power is restored to the smartsocket the bat- tery voltage is checked with a precision comparator. if the battery supply is less than 2.0 volts, the second memory access to the smartsocket is inhibited. battery status can, therefore, be determined by a threestep process. first, a read cycle is performed to any location in the memory, in order to save the contents of that loca- tion. a subsequent write cycle can then be executed to the same memory location, altering the data. if the next read cycle fails to verify the written data, then the battery voltage is less than 2.0v and data is in danger of being corrupted. the fifth function the smartsocket provides is battery redundancy. in many applications, data integrity is par- amount. in these applications it is desirable to use two batteries to ensure reliability. the DS1213B smart- socket provides two batteries and an internal isolation switch to select between them. during battery back up, the battery with the highest voltage is selected for use. if one battery fails, the other automatically takes over. the switch between batteries is transparent to the user. a battery status warning will occur if both batteries are less than 2.0 volts. each of the two internal lithium cells has a 45 mah capacity. note: as shipped from dallas semiconductor, battery voltage cannot be measured on the v cc socket contact. only after v cc has been applied to the device for the first time and then removed will the battery voltage be present on socket contacts 28, 26 and 20.
DS1213B 031998 3/6 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 40 c to +70 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes pin 26 l, pin 28 l supply voltage v cc 4.75 5.0 5.5 v 1, 3 logic 1 pin 20 l v ih 2.2 v cc +0.3 v 1, 3 logic 0 pin 20 l v il 0.3 + 0.8 v 1, 3 dc electrical characteristics (0 c to 70 c; v cc = 4.75 to 5.5v) parameter symbol min typ max units notes pin 26 l, pin 28 l supply current i cc 5 ma 3, 4, 5 pin 26 u, pin 28 u supply voltage v cco v cc 0.2 v 1, 3, 8 pin 26 u, pin 28 u supply current i cco 80 ma 3, 8 pin 20 l ce input leakage i il 1.0 +1.0 m a 3, 4 pin 20 u ce output @ 2.4 v i oh 1.0 ma 2, 3 pin 20 u ce output @ .4v i ol 4.0 ma 2, 3 dc electrical characteristics (0 c to 70 c; v cc < 4.5v) pin 20 u output v ohl v cc 0.2 v bat -0.2 v 1, 3 pin 26 u, pin 28u battery current i bat 1 m a 3, 6 pin 26 u, pin 28 u battery voltage v bat 2 3 3.6 v 1, 3 capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance pin 20 l c in 5 pf 3 output capacitance pin 20 u c out 7 pf 3
DS1213B 031998 4/6 ac electrical characteristics (0 c to 70 c; v cc = 4.75 to 5.5v) parameter symbol min typ max units notes ce propagation delay t pd 5 10 20 ns 2,9 ce high to power fail t pf 0 ns ac electrical characteristics (0 c to 70 c; v cci < 4.75 v) recovery at powerup t rec 2 80 125 ms v cc slew rate 4.75 4.5 v t f 300 m s v cc slew rate 4.5 3 v t fb 10 m s v cc slew rate 4.54.75 v t r 0 m s ce pulse width t ce 1.5 m s 7 timing diagram: powerdown 4.75v 4.5v 3.0v ce pin 20 l ce pin 20 u t ce t ce v cc pin 26 l, pin 28 l v ih v il t pd v il v ih t pf v bat - 0.2v t f t fb
DS1213B 031998 5/6 timing diagram: powerup 4.75v 4.5v ce pin 20 l v ih v il v bat - 0.2v ce pin 20 u v il t rec t pd t r v cc pin 26 l, pin 28 l warnings: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. water washing for flux removal will discharge internal lithium source because exposed voltage pins are present. notes: 1. all voltages are referenced to ground. 2. measured with a load as shown in figure 1. 3. pin locations are designated auo (for upper) when a parameter definition refers to the socket receptacle and alo (for lower) when a parameter definition refers to the socket pin. 4. no memory inserted in the socket. 5. pin 26 l may be connected to v cc or left disconnected at the pc board. 6. i bat is the maximum load current which a correctly installed memory can use in the data retention mode and meet data retention expectations of more than 10 years at 25 c. 7. t ce max. must be met to ensure data integrity on power loss. 8. v cc is within nominal limits and a memory is installed in the socket. 9. input pulse rise and fall times equal 10 ns.
13 equal spaces at 0.100 + 0 .010 tna 28 15 114 a g f c k d dim min max 28pin pkg a in. 1.380 1.420 mm 35.05 36.07 b in. 0.690 0.720 mm 17.53 18.29 c in. 0.420 0.470 mm 10.16 11.94 d in. 0.035 0.065 mm 0.89 1.65 e in. 0.055 0.075 mm 1.39 1.90 f in. 0.120 0.160 mm 3.04 4.06 g in. 0.090 0.110 mm 2.29 2.79 h in. 0.590 0.630 mm 14.99 16.00 j in. 0.008 0.012 mm 0.20 0.30 k in. 0.015 0.021 mm 0.38 0.53 l in. 0.380 0.420 mm 9.65 10.67 h j e b l DS1213B 031998 6/6 output load figure 1 50 pf d.u.t. 1.1k ohms +5 volts 680 ohms DS1213B intelligent socket 28 pin (for 600mil dip)
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